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preliminary publication# 21445 rev: b amendment/ +2 issue date: april 1998 am29f040b 4 megabit (512 k x 8-bit) cmos 5.0 volt-only, uniform sector flash memory distinctive characteristics n 5.0 v 10% for read and write operations minimizes system level power requirements n manufactured on 0.35 m process technology compatible with 0.5 m am29f040 device n high performance access times as fast as 55 ns n low power consumption 20 ma typical active read current 30 ma typical program/erase current 1 a typical standby current (standard access time to active mode) n flexible sector architecture 8 uniform sectors of 64 kbytes each any combination of sectors can be erased supports full chip erase sector protection: a hardware method of locking sectors to prevent any program or erase operations within that sector n embedded algorithms embedded erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors embedded program algorithm automatically writes and verifies bytes at specified addresses n minimum 1,000,000 program/erase cycles per sector guaranteed n package options 32-pin plcc, tsop, or pdip n compatible with jedec standards pinout and software compatible with single-power-supply flash standard superior inadvertent write protection n data# polling and toggle bits provides a software method of detecting program or erase cycle completion n erase suspend/erase resume suspends a sector erase operation to read data from, or program data to, a non-erasing sector, then resumes the erase operation
2 am29f040b preliminary general description the am29f040b is a 4 mbit, 5.0 volt-only flash mem- ory organized as 524,288 kbytes of 8 bits each. the 512 kbytes of data are divided into eight sectors of 64 kbytes each for flexible erase capability. the 8 bits of data appear on dq0Cdq7. the am29f040b is offered in 32-pin plcc, tsop, and pdip packages. this de- vice is designed to be programmed in-system with the standard system 5.0 volt v cc supply. a 12.0 volt v pp is not required for write or erase operations. the device can also be programmed in standard eprom pro- grammers. this device is manufactured using amds 0.35 m process technology, and offers all the features and ben- efits of the am29f040, which was manufactured using 0.5 m process technology. in addtion, the am29f040b has a second toggle bit, dq2, and also offers the ability to program in the erase suspend mode. the standard am29f040b offers access times of 55, 70, 90, 120, and 150 ns, allowing high-speed micropro- cessors to operate without wait states. to eliminate bus contention the device has separate chip enable (ce#), write enable (we#) and output enable (oe#) controls. the device requires only a single 5.0 volt power sup- ply for both read and write functions. internally gener- ated and regulated voltages are provided for the program and erase operations. the device is entirely command set compatible with the jedec single-power-supply flash standard . com- mands are written to the command register using stan- dard microprocessor write timings. register contents serve as input to an internal state-machine that con- trols the erase and programming circuitry. write cycles also internally latch addresses and data needed for the programming and erase operations. reading data out of the device is similar to reading from other flash or eprom devices. device programming occurs by executing the program command sequence. this initiates the embedded program algorithman internal algorithm that auto- matically times the program pulse widths and verifies proper cell margin. device erasure occurs by executing the erase com- mand sequence. this initiates the embedded erase algorithman internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. during erase, the device automatically times the erase pulse widths and verifies proper cell margin. the host system can detect whether a program or erase operation is complete by reading the dq7 (data# polling) and dq6 (toggle) status bits . after a program or erase cycle has been completed, the device is ready to read array data or accept another command. the sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. the device is fully erased when shipped from the factory. hardware data protection measures include a low v cc detector that automatically inhibits write opera- tions during power transitions. the hardware sector protection feature disables both program and erase operations in any combination of the sectors of mem- ory. this can be achieved via programming equipment. the erase suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. true background erase can thus be achieved. the system can place the device into the standby mode . power consumption is greatly reduced in this mode. amds flash technology combines years of flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effective- ness. the device electrically erases all bits within a sector simultaneously via fowler-nor dheim tunnel- ing. the data is programmed using hot electron injec- tion.
am29f040b 3 preliminary product selector guide note: see the ac characteristics section for more information. block diagram family part number am29f040b speed option v cc = 5.0 v 5% -55 v cc = 5.0 v 10% -70 -90 -120 -150 max access time, ns (t acc ) 55 70 90 120 150 max ce# access time, ns (t ce ) 55 70 90 120 150 max oe# access time, ns (t oe ) 2530355055 erase voltage generator y-gating cell matrix x-decoder y-decoder address latch chip enable output enable logic pgm voltage generator timer v cc detector state control command register we# ce# oe# a0Ca18 stb stb dq0Cdq7 v cc v ss 21445b-1 data latch input/output buffers
4 am29f040b preliminary connection diagrams 21445b-2 v cc we# a17 a14 a13 a8 a9 a11 oe# a10 ce# dq7 dq6 dq5 dq4 dq3 a18 a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 pdip 5 6 7 8 9 10 11 12 13 17 18 19 20 16 15 14 29 28 27 26 25 24 23 22 21 13130 2 3 432 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 v ss dq3 dq4 dq5 dq6 a14 a13 a8 a9 a11 oe# a10 ce# dq7 a12 a15 a16 a18 v cc we# a17 21445b-3 plcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a11 a9 a8 a13 a14 a17 we# v cc a18 a16 a15 a12 a7 a6 a5 a4 oe# a10 ce# dq7 dq6 dq5 dq4 dq3 v ss dq2 dq1 dq0 a0 a1 a2 a3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a11 a9 a8 a13 a14 a17 we# v cc a18 a16 a15 a12 a7 a6 a5 a4 oe# a10 ce# dq7 dq6 dq5 dq4 dq3 v ss dq2 dq1 dq0 a0 a1 a2 a3 21445b-4 32-pin standard tsop 32-pin reverse tsop
am29f040b 5 preliminary pin configuration a0Ca18 = address inputs dq0Cdq7 = data input/output ce# = chip enable we# = write enable oe# = output enable v ss = device ground v cc = +5.0 v single power supply (see product selector guide for device speed ratings and voltage supply tolerances) logic symbol ordering information standard products amd standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of the following: valid combinations valid combinations list configurations planned to be sup- ported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly released combinations. 19 8 dq0Cdq7 a0Ca18 ce# oe# we# 21445b-5 device number/description am29f040b 4 megabit (512 k x 8-bit) cmos 5.0 volt-only sector erase flash memory 5.0 v read, program, and erase am29f040b -55 e c b optional processing blank = standard processing b = burn-in (contact an amd representative for more information) temperature range c = commercial (0 c to +70 c) i= industrial (C40 c to +85 c) e = extended (C55 c to +125 c) package type p = 32-pin plastic dip (pd 032) j = 32-pin rectangular plastic leaded chip carrier (pl 032) e = 32-pin thin small outline package (tsop) standard pinout (ts 032) f = 32-pin thin small outline package (tsop) reverse pinout (tsr032) speed option see product selector guide and valid combinations valid combinations am29f040b-55 jc, ji, je, ec, ei, ee, fc, fi, fe am29f040b-70 am29f040b-90 pc, pi, pe, jc, ji, je, ec, ei, ee, fc, fi, fe am29f040b-120 am29f040b-150
6 am29f040b preliminary device bus operations this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the command register it- self does not occupy any addressable memory loca- tion. the register is composed of latches that store the commands, along with the address and data informa- tion needed to execute the command. the contents of the register serve as inputs to the internal state ma- chine. the state machine outputs dictate the function of the device. the appropriate device bus operations table lists the inputs and control levels required, and the resulting output. the following subsections describe each of these operations in further detail. table 1. am29f040b device bus operations legend: l = logic low = v il , h = logic high = v ih , v id = 12.0 0.5 v, x = dont care, d in = data in, d out = data out, a in = address in note: see the section on sector protection for more information. requirements for reading array data to read array data from the outputs, the system must drive the ce# and oe# pins to v il . ce# is the power control and selects the device. oe# is the output control and gates array data to the output pins. we# should re- main at v ih . the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the mem- ory content occurs during the power transition. no command is necessary in this mode to obtain array data. standard microprocessor read cycles that as- sert valid addresses on the device address inputs produce valid data on the device data outputs. the device remains enabled for read access until the command register contents are altered. see reading array data for more information. refer to the ac read operations table for timing specifica- tions and to the read operations timings diagram for the timing waveforms. i cc1 in the dc characteristics table represents the active current specification for reading array data. writing commands/command sequences to write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive we# and ce# to v il , and oe# to v ih . an erase operation can erase one sector, multiple sec- tors, or the entire device. the sector address tables in- dicate the address space that each sector occupies. a sector address consists of the address bits required to uniquely select a sector. see the command defini- tions section for details on erasing a sector or the en- tire chip, or suspending/resuming the erase operation. after the system writes the autoselect command se- quence, the device enters the autoselect mode. the system can then read autoselect codes from the inter- nal register (which is separate from the memory array) on dq7Cdq0. standard read cycle timings apply in this mode. refer to the autoselect mode and autoselect command sequence sections for more information. i cc2 in the dc characteristics table represents the ac- tive current specification for the write mode. the ac characteristics section contains timing specification tables and timing diagrams for write operations. program and erase operation status during an erase or program operation, the system may check the status of the operation by reading the status bits on dq7Cdq0. standard read cycle timings and i cc read specifications apply. refer to write operation status for more information, and to each ac charac- teristics section for timing diagrams. standby mode when the system is not reading or writing to the device, it can place the device in the standby mode. in this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, inde- pendent of the oe# input. operation ce# oe# we# a0Ca20 dq0Cdq7 read l l h a in d out write l h l a in d in cmos standby v cc 0.5 v x x x high-z ttl standby h x x x high-z output disable l h h x high-z
am29f040b 7 preliminary the device enters the cmos standby mode when the ce# pin is held at v cc 0.5 v. (note that this is a more restricted voltage range than v ih .) the device enters the ttl standby mode when ce# is held at v ih . the device requires the standard access time (t ce ) before it is ready to read data. if the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. i cc3 in the dc characteristics tables represents the standby current specification. output disable mode when the oe# input is at v ih , output from the device is disabled. the output pins are placed in the high imped- ance state. table 2. sector addresses table note: all sectors are 64 kbytes in size. autoselect mode the autoselect mode provides manufacturer and de- vice identification, and sector protection verification, through identifier codes output on dq7Cdq0. this mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. however, the autoselect codes can also be accessed in-system through the command register. when using programming equipment, the autoselect mode requires v id (11.5 v to 12.5 v) on address pin a9. address pins a6, a1, and a0 must be as shown in autoselect codes (high voltage method) table. in addi- tion, when verifying sector protection, the sector ad- dress must appear on the appropriate highest order address bits. refer to the corresponding sector ad- dress tables. the command definitions table shows the remaining address bits that are dont care. when all necessary bits have been set as required, the program- ming equipment may then read the corresponding identifier code on dq7Cdq0. to access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in the command defini- tions table. this method does not require v id . see command definitions for details on using the autose- lect mode. sector a18 a17 a16 address range sa0 0 0 0 00000hC0ffffh sa1 0 0 1 10000hC1ffffh sa2 0 1 0 20000hC2ffffh sa3 0 1 1 30000hC3ffffh sa4 1 0 0 40000hC4ffffh sa5 1 0 1 50000hC5ffffh sa6 1 1 0 60000hC6ffffh sa7 1 1 1 70000hC7ffffh
8 am29f040b preliminary table 3. am29f040b autoselect codes (high voltage method) sector protection/unprotection the hardware sector protection feature disables both program and erase operations in any sector. the hardware sector unprotection feature re-enables both program and erase operations in previously pro- tected sectors. sector protection/unprotection must be implemented using programming equipment. the procedure re- quires a high voltage (v id ) on address pin a9 and the control pins. details on this method are provided in a supplement, publication number 19957. contact an amd representative to obtain a copy of the appropriate document. the device is shipped with all sectors unprotected. amd offers the option of programming and protecting sectors at its factory prior to shipping the device through amds expressflash? service. contact an amd representative for details. it is possible to determine whether a sector is protected or unprotected. see autoselect mode for details. hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to the command defi- nitions table). in addition, the following hardware data protection measures prevent accidental erasure or pro- gramming, which might otherwise be caused by spuri- ous system level signals during v cc power-up and power-down transitions, or from system noise. low v cc write inhibit when v cc is less than v lko , the device does not ac- cept any write cycles. this protects data during v cc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets. subsequent writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control pins to prevent uninten- tional writes when v cc is greater than v lko . write pulse glitch protection noise pulses of less than 5 ns (typical) on oe#, ce# or we# do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce# = v ih or we# = v ih . to initiate a write cycle, ce# and we# must be a logical zero while oe# is a logical one. power-up write inhibit if we# = ce# = v il and oe# = v ih during power up, the device does not accept commands on the rising edge of we#. the internal state machine is automatically reset to reading array data on power-up. command definitions writing specific address and data commands or se- quences into the command register initiates device op- erations. the command definitions table defines the valid register command sequences. writing incorrect address and data values or writing them in the im- proper sequence resets the device to reading array data. all addresses are latched on the falling edge of we# or ce#, whichever happens later. all data is latched on the rising edge of we# or ce#, whichever happens first. refer to the appropriate timing diagrams in the ac characteristics section. reading array data the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. the device is also ready to read array data after completing an embedded program or em- bedded erase algorithm. after the device accepts an erase suspend command, the device enters the erase suspend mode. the sys- tem can read array data using the standard read tim- ings, except that if it reads at an address within erase- suspended sectors, the device outputs status data. after completing a programming operation in the erase suspend mode, the system may once again read array description a18Ca16 a15Ca10 a9 a8Ca7 a6 a5Ca2 a1 a0 identifier code on dq7-dq0 manufacturer id : amd x x v id xv il xv il v il 01h device id: am29f040b x x v id xv il xv il v ih a4h sector protection verification sector address xv id xv il xv ih v il 01h (protected) 00h (unprotected)
am29f040b 9 preliminary data with the same exception. see erase suspend/ erase resume commands for more information on this mode. the system must issue the reset command to re-en- able the device for reading array data if dq5 goes high, or while in the autoselect mode. see the reset com- mand section, next. see also requirements for reading array data in the device bus operations section for more information. the read operations table provides the read parame- ters, and read operation timings diagram shows the timing diagram. reset command writing the reset command to the device resets the de- vice to reading array data. address bits are dont care for this command. the reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. this resets the device to reading array data. once erasure begins, however, the device ig- nores reset commands until the operation is complete. the reset command may be written between the se- quence cycles in a program command sequence be- fore programming begins. this resets the device to reading array data (also applies to programming in erase suspend mode). once programming begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the se- quence cycles in an autoselect command sequence. once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during erase suspend). if dq5 goes high during a program or erase operation, writing the reset command returns the device to read- ing array data (also applies during erase suspend). autoselect command sequence the autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. the command definitions table shows the address and data requirements. this method is an alternative to that shown in the autoselect codes (high voltage method) table, which is intended for prom program- mers and requires v id on address bit a9. the autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. the device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence. a read cycle at address xx00h or retrieves the manu- facturer code. a read cycle at address xx01h returns the device code. a read cycle containing a sector ad- dress (sa) and the address 02h in returns 01h if that sector is protected, or 00h if it is unprotected. refer to the sector address tables for valid sector addresses. the system must write the reset command to exit the autoselect mode and return to reading array data. byte program command sequence programming is a four-bus-cycle operation. the pro- gram command sequence is initiated by writing two un- lock write cycles, followed by the program set-up command. the program address and data are written next, which in turn initiate the embedded program al- gorithm. the system is not required to provide further controls or timings. the device automatically provides internally generated program pulses and verify the pro- grammed cell margin. the command definitions take shows the address and data requirements for the byte program command sequence. when the embedded program algorithm is complete, the device then returns to reading array data and ad- dresses are no longer latched. the system can deter- mine the status of the program operation by using dq7 or dq6. see write operation status for information on these status bits. any commands written to the device during the em- bedded program algorithm are ignored. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from a 0 back to a 1. attempting to do so may halt the operation and set dq5 to 1, or cause the data# polling algorithm to indicate the operation was suc- cessful. however, a succeeding read will show that the data is still 0. only erase operations can convert a 0 to a 1.
10 am29f040b preliminary note: see the appropriate command definitions table for program command sequence. figure 1. program operation chip erase command sequence chip erase is a six-bus-cycle operation. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algo- rithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any con- trols or timings during these operations. the command definitions table shows the address and data require- ments for the chip erase command sequence. any commands written to the chip during the embed- ded erase algorithm are ignored. the system can determine the status of the erase operation by using dq7, dq6, or dq2. see write operation status for information on these status bits. when the embedded erase algorithm is com- plete, the device returns to reading array data and addresses are no longer latched. figure 2 illustrates the algorithm for the erase opera- tion. see the erase/program operations tables in ac characteristics for parameters, and to the chip/sector erase operation timings for timing waveforms. sector erase command sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two un- lock cycles, followed by a set-up command. two addi- tional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. the command definitions table shows the address and data requirements for the sec- tor erase command sequence. the device does not require the system to preprogram the memory prior to erase. the embedded erase algo- rithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or tim- ings during these operations. after the command sequence is written, a sector erase time-out of 50 s begins. during the time-out period, additional sector addresses and sector erase com- mands may be written. loading the sector erase buffer may be done in any sequence, and the number of sec- tors may be from one sector to all sectors. the time be- tween these additional cycles must be less than 50 s, otherwise the last address and command might not be accepted, and erasure may begin. it is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. the interrupts can be re-enabled after the last sector erase command is written. if the time between additional sector erase commands can be assumed to be less than 50 s, the system need not monitor dq3. any command other than sector erase or erase suspend during the time-out period resets the device to reading array data. the system must rewrite the command sequence and any additional sector addresses and commands. the system can monitor dq3 to determine if the sector erase timer has timed out. (see the dq3: sector erase timer section.) the time-out begins from the rising edge of the final we# pulse in the command sequence. once the sector erase operation has begun, only the erase suspend command is valid. all other commands are ignored. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. the system can determine the sta- tus of the erase operation by using dq7, dq6, or dq2. refer to write operation status for information on these status bits. start write program command sequence data poll from system verify data? no yes last address? no yes programming completed increment address embedded program algorithm in progress 21445b-6
am29f040b 11 preliminary figure 2 illustrates the algorithm for the erase opera- tion. refer to the erase/program operations tables in the ac characteristics section for parameters, and to the sector erase operations timing diagram for timing waveforms. erase suspend/erase resume commands the erase suspend command allows the system to in- terrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. this command is valid only during the sector erase operation, including the 50 s time-out period during the sector erase command sequence. the erase suspend command is ignored if written during the chip erase operation or embedded program algo- rithm. writing the erase suspend command during the sector erase time-out immediately terminates the time-out period and suspends the erase operation. ad- dresses are dont-cares when writing the erase sus- pend command. when the erase suspend command is written during a sector erase operation, the device requires a maximum of 20 s to suspend the erase operation. however, when the erase suspend command is written during the sector erase time-out, the device immediately ter- minates the time-out period and suspends the erase operation. after the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. (the device erase suspends all sectors selected for erasure.) normal read and write timings and command definitions apply. reading at any address within erase-suspended sec- tors produces status data on dq7Cdq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is actively erasing or is erase-suspended. see write operation status for information on these status bits. after an erase-suspended program operation is com- plete, the system can once again read array data within non-suspended sectors. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard program oper- ation. see write operation status for more informa- tion. the system may also write the autoselect command sequence when the device is in the erase suspend mode. the device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. when the device exits the autoselect mode, the device reverts to the erase suspend mode, and is ready for another valid operation. see autoselect command sequence for more information. the system must write the erase resume command (address bits are dont care) to exit the erase suspend mode and continue the sector erase operation. further writes of the resume command are ignored. another erase suspend command can be written after the de- vice has resumed erasing. notes: 1. see the appropriate command definitions table for erase command sequence. 2. see dq3: sector erase timer for more information. figure 2. erase operation start write erase command sequence data poll from system data = ffh? no yes erasure completed embedded erase algorithm in progress 21445b-7
12 am29f040b preliminary table 4. am29f040b command definitions legend: x = dont care ra = address of the memory location to be read. rd = data read from location ra during read operation. pa = address of the memory location to be programmed. addresses latch on the falling edge of the we# or ce# pulse, whichever happens later. pd = data to be programmed at location pa. data latches on the rising edge of we# or ce# pulse, whichever happens first. sa = address of the sector to be verified (in autoselect mode) or erased. address bits a18Ca16 select a unique sector. notes: 1. see table 1 for description of bus operations. 2. all values are in hexadecimal. 3. except when reading array or autoselect data, all bus cycles are write operations. 4. address bits a18Ca11 are dont cares for unlock and command cycles, unless sa or pa required. 5. no unlock or command cycles required when reading array data. 6. the reset command is required to return to reading array data when device is in the autoselect mode, or if dq5 goes high (while the device is providing status data). 7. the fourth cycle of the autoselect command sequence is a read cycle. 8. the data is 00h for an unprotected sector and 01h for a protected sector. see autoselect command sequence for more information. 9. the system may read and program in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation. 10. the erase resume command is valid only during the erase suspend mode. command sequence (note 1) bus cycles (notes 2C4) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read (note 5) 1 ra rd reset (note 6) 1 xxx f0 autoselect (note 7) manufacturer id 4 555 aa 2aa 55 555 90 x00 01 device id 4 555 aa 2aa 55 555 90 x01 a4 sector protect verify (note 8) 4 555 aa 2aa 55 555 90 sa x02 xx00 xx01 program 4 555 aa 2aa 55 555 a0 pa pd chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 erase suspend (note 9) 1 xxx b0 erase resume (note 10) 1 xxx 30 cycles
am29f040b 13 preliminary write operation status the device provides several bits to determine the sta- tus of a write operation: dq2, dq3, dq5, dq6, and dq7. table 5 and the following subsections describe the functions of these bits. dq7 and dq6 each offer a method for determining whether a program or erase operation is complete or in progress. these three bits are discussed first. dq7: data# polling the data# polling bit, dq7, indicates to the host system whether an embedded algorithm is in progress or completed, or whether the device is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the program or erase command sequence. during the embedded program algorithm, the device outputs on dq7 the complement of the datum pro- grammed to dq7. this dq7 status also applies to pro- gramming during erase suspend. when the embedded program algorithm is complete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a program address falls within a protected sector, data# polling on dq7 is active for ap- proximately 2 s, then the device returns to reading array data. during the embedded erase algorithm, data# polling produces a 0 on dq7. when the embedded erase al- gorithm is complete, or if the device enters the erase suspend mode, data# polling produces a 1 on dq7. this is analogous to the complement/true datum output described for the embedded program algorithm: the erase function changes all the bits in a sector to 1; prior to this, the device outputs the complement, or 0. the system must provide an address within any of the sectors selected for erasure to read valid status in- formation on dq7. after an erase command sequence is written, if all sec- tors selected for erasing are protected, data# polling on dq7 is active for approximately 100 s, then the de- vice returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the se- lected sectors that are protected. when the system detects dq7 has changed from the complement to true data, it can read valid data at dq7Cdq0 on the following read cycles. this is be- cause dq7 may change asynchronously with dq0Cdq6 while output enable (oe#) is asserted low. the data# polling timings (during embedded algo- rithms) figure in the ac characteristics section illus- trates this. table 5 shows the outputs for data# polling on dq7. figure 3 shows the data# polling algorithm. dq7 = data? yes no no dq5 = 1? no yes yes fail pass read dq7Cdq0 addr = va read dq7Cdq0 addr = va dq7 = data? start notes: 1. va = valid address for programming. during a sector erase operation, a valid address is an address within any sector selected for erasure. during chip erase, a valid address is any non-protected sector address. 2. dq7 should be rechecked even if dq5 = 1 because dq7 may change simultaneously with dq5. 21445b-8 figure 3. data# polling algorithm
14 am29f040b preliminary dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase op- eration), and during the sector erase time-out. during an embedded program or erase algorithm op- eration, successive read cycles to any address cause dq6 to toggle. (the system may use either oe# or ce# to control the read cycles.) when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 tog- gles for approximately 100 s, then returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unpro- tected sectors, and ignores the selected sectors that are protected. the system can use dq6 and dq2 together to deter- mine whether a sector is actively erasing or is erase- suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the device enters the erase suspend mode, dq6 stops toggling. however, the system must also use dq2 to determine which sectors are erasing or erase-suspended. alternatively, the system can use dq7 (see the subsection on dq7: data# polling). if a program address falls within a protected sector, dq6 toggles for approximately 2 s after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded pro- gram algorithm is complete. the write operation status table shows the outputs for toggle bit i on dq6. refer to figure 4 for the toggle bit algorithm, and to the toggle bit timings figure in the ac characteristics section for the timing diagram. the dq2 vs. dq6 figure shows the differences be- tween dq2 and dq6 in graphical form. see also the subsection on dq2: toggle bit ii. dq2: toggle bit ii the toggle bit ii on dq2, when used with dq6, indi- cates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that have been selected for era- sure. (the system may use either oe# or ce# to con- trol the read cycles.) but dq2 cannot distinguish whether the sector is actively erasing or is erase-sus- pended. dq6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for era- sure. thus, both status bits are required for sector and mode information. refer to table 5 to compare outputs for dq2 and dq6. figure 4 shows the toggle bit algorithm in flowchart form, and the section dq2: toggle bit ii explains the algorithm. see also the dq6: toggle bit i subsection. refer to the toggle bit timings figure for the toggle bit timing diagram. the dq2 vs. dq6 figure shows the dif- ferences between dq2 and dq6 in graphical form. reading toggle bits dq6/dq2 refer to figure 4 for the following discussion. when- ever the system initially begins reading toggle bit sta- tus, it must read dq7Cdq0 at least twice in a row to determine whether a toggle bit is toggling. typically, a system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the sys- tem can read array data on dq7Cdq0 on the following read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped tog- gling just as dq5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially de- termines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cycles, de- termining the status as described in the previous para- graph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of figure 4). dq5: exceeded timing limits dq5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. under these conditions dq5 produces a 1. this is a failure condition that indicates the program or erase cycle was not successfully completed.
am29f040b 15 preliminary the dq5 failure condition may appear if the system tries to program a 1 to a location that is previously pro- grammed to 0. only an erase operation can change a 0 back to a 1. under this condition, the device halts the operation, and when the operation has ex- ceeded the timing limits, dq5 produces a 1. under both these conditions, the system must issue the reset command to return the device to reading array data. dq3: sector erase timer after writing a sector erase command sequence, the system may read dq3 to determine whether or not an erase operation has begun. (the sector erase timer does not apply to the chip erase command.) if addi- tional sectors are selected for erasure, the entire time- out also applies after each additional sector erase command. when the time-out is complete, dq3 switches from 0 to 1. the system may ignore dq3 if the system can guarantee that the time between ad- ditional sector erase commands will always be less than 50 s. see also the sector erase command se- quence section. after the sector erase command sequence is written, the system should read the status on dq7 (data# poll- ing) or dq6 (toggle bit i) to ensure the device has ac- cepted the command sequence, and then read dq3. if dq3 is 1, the internally controlled erase cycle has be- gun; all further commands (other than erase suspend) are ignored until the erase operation is complete. if dq3 is 0, the device will accept additional sector erase commands. to ensure the command has been accepted, the system software should check the status of dq3 prior to and following each subsequent sector erase command. if dq3 is high on the second status check, the last command might not have been ac- cepted. table 5 shows the outputs for dq3. start no yes yes dq5 = 1? no yes toggle bit = toggle? no program/erase operation not complete, write reset command program/erase operation complete read dq7Cdq0 toggle bit = toggle? read dq7Cdq0 twice read dq7Cdq0 notes: 1. read toggle bit twice to determine whether or not it is toggling. see text. 2. recheck toggle bit because it may stop toggling as dq5 changes to 1. see text. 21445b-9 figure 4. toggle bit algorithm (notes 1, 2) note 1
16 am29f040b preliminary table 5. write operation status notes: 1. dq7 and dq2 require a valid address when reading status information. refer to the appropriate subsection for further details. 2. dq5 switches to 1 when an embedded program or embedded erase operation has exceeded the maximum timing limits. see dq5: exceeded timing limits for more information. operation dq7 (note 1) dq6 dq5 (note 2) dq3 dq2 (note 1) standard mode embedded program algorithm dq7# toggle 0 n/a no toggle embedded erase algorithm 0 toggle 0 1 toggle erase suspend mode reading within erase suspended sector 1 no toggle 0 n/a toggle reading within non-erase suspended sector data data data data data erase-suspend-program dq7# toggle 0 n/a n/a
am29f040b 17 preliminary absolute maximum ratings storage temperature plastic packages . . . . . . . . . . . . . . . C65c to +125c ambient temperature with power applied. . . . . . . . . . . . . . C55c to +125c voltage with respect to ground v cc (note 1) . . . . . . . . . . . . . . . . . C2.0 v to 7.0 v a9, oe# (note 2) . . . . . . . . . . . . . C2.0 v to 12.5 v all other pins (note 1) . . . . . . . . . . C2.0 v to 7.0 v output short circuit current (note 3) . . . . . . 200 ma notes: 1. minimum dc voltage on input or i/o pins is C0.5 v. during voltage transitions, inputs may undershoot v ss to C2.0 v for periods of up to 20 ns. see figure 5. maximum dc voltage on input and i/o pins is v cc + 0.5 v. during voltage transitions, input and i/o pins may overshoot to v cc + 2.0 v for periods up to 20 ns. see figure 6. 2. minimum dc input voltage on a9 pin is C0.5 v. during voltage transitions, a9 and oe# may undershoot v ss to C2.0 v for periods of up to 20 ns. see figure 5. maximum dc input voltage on a9 and oe# is 12.5 v which may overshoot to 13.5 v for periods up to 20 ns. 3. no more than one output shorted to ground at a time. duration of the short circuit should not be greater than one second. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the op- erational sections of this specification is not implied. expo- sure of the device to absolute maximum rating conditions for extended periods may affect device reliability. figure 5. maximum negative overshoot waveform figure 6. maximum positive overshoot waveform operating ranges commer cial (c) devices ambient temperature (t a ) . . . . . . . . . . . 0 c to +70 c industrial (i) devices ambient temperature (t a ) . . . . . . . . . C40c to +85c extended (e) devices ambient temperature (t a ) . . . . . . . . C55c to +125c v cc supply voltages v cc for 5% devices . . . . . . . . . . .+4.75 v to +5.25 v v cc for 10% devices . . . . . . . . . . . .+4.5 v to +5.5 v operating ranges define those limits between which the functionality of the device is guaranteed. 20 ns 20 ns +0.8 v C0.5 v 20 ns C2.0 v 21445b-10 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 2.0 v 21445b-11
18 am29f040b preliminary dc characteristics ttl/nmos compatible cmos compatible notes for dc characteristics (both tables): 1. the i cc current listed includes both the dc operating current and the frequency dependent component (at 6 mhz). the frequency component typically is less than 2 ma/mhz, with oe# at v ih . 2. i cc active while embedded algorithm (program or erase) is in progress. 3. not 100% tested. 4. for cmos mode only, i cc3 = 20 a max at extended temperatures (> +85c). parameter symbol parameter description test description min typ max unit i li input load current v in = v ss to v cc , v cc = v cc max 1.0 a i lit a9 input load current v cc = v cc max, a9 = 12.5 v 50 a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1.0 a i cc1 v cc active read current (note 1) ce# = v il, oe# = v ih 20 30 ma i cc2 v cc active write (program/erase) current (notes 2, 3) ce# = v il, oe# = v ih 30 40 ma i cc3 v cc standby current v cc = v cc max, ce# = v ih 0.4 1.0 ma v il input low level C0.5 0.8 v v ih input high level 2.0 v cc + 0.5 v v id voltage for autoselect and sector protect v cc = 5.25 v 10.5 12.5 v v ol output low voltage i ol = 12 ma, v cc = v cc min 0.45 v v oh output high level i oh = C2.5 ma, v cc = v cc min 2.4 v v lko low v cc lock-out voltage 3.2 4.2 v parameter symbol parameter description test description min typ max unit i li input load current v in = v ss to v cc , v cc = v cc max 1.0 a i lit a9 input load current v cc = v cc max, a9 = 12.5 v 50 a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1.0 a i cc1 v cc active read current (note 1) ce# = v il, oe# = v ih 20 30 ma i cc2 v cc active program/erase current (notes 2, 3) ce# = vil, oe# = vih 30 40 ma i cc3 v cc standby current (note 4) v cc = v cc max, ce# = v cc 0.5 v 1 5 a v il input low level C0.5 0.8 v v ih input high level 0.7 x v cc v cc + 0.3 v v id voltage for autoselect and sector protect v cc = 5.25 v 10.5 12.5 v v ol output low voltage i ol = 12.0 ma, v cc = v cc min 0.45 v v oh1 output high voltage i oh = C2.5 ma, v cc = v cc min 0.85 v cc v v oh2 i oh = C100 m a, v cc = v cc min v cc C0.4 v v lko low v cc lock-out voltage 3.2 4.2 v
am29f040b 19 preliminary test conditions table 6. test specifications key to switching waveforms 2.7 k w c l 6.2 k w 5.0 v device under te s t 21445b-12 fi g ure 7. test setu p note: diodes are in3064 or equivalent test condition -55 all others unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 30 100 pf input rise and fall times 5 20 ns input pulse levels 0.0C3.0 0.45C2.4 v input timing measurement reference levels 1.5 0.8 v output timing measurement reference levels 1.5 2.0 v ks000010-pal waveform inputs outputs steady changing from h to l changing from l to h dont care, any change permitted changing, state unknown does not apply center line is high impedance state (high z)
20 am29f040b preliminary ac characteristics read only operations notes: 1. see figure 7 and table 6 for test conditions. 2. output driver disable time. 3. not 100% tested. parameter symbols description test setup speed options (note 1) unit jedec standard -55 -70 -90 -120 -150 t avav t rc read cycle time (note 3) min 55 70 90 120 150 ns t avqv t acc address to output delay ce# = v il, oe# = v il max 55 70 90 120 150 ns t elqv t ce chip enable to output delay oe# = v il max 55 70 90 120 150 ns t glqv t oe output enable to output delay max 30 30 35 50 55 ns t oeh output enable hold time (note 3) read min00000ns toggle and data# polling min1010101010ns t ehqz t df chip enable to output high z (notes 2, 3) max1820203035ns t ghqz t df output enable to output high z (notes 2, 3) 18 20 20 30 35 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first min00000ns t ce outputs we# addresses ce# oe# high z output valid high z addresses stable t rc t acc t oeh t oe 0 v t df t oh 21445b-13 figure 8. read operation timings
am29f040b 21 preliminary ac characteristics erase and program operations notes: 1. not 100% tested. 2. see the erase and programming performance section for more information. parameter symbols description speed options unit jedec std. -55 -70 -90 -120 -150 t avav t wc write cycle time (note 1) min 55 70 90 120 150 ns t avwl t as address setup time min 0 ns t wlax t ah address hold time min 40 45 45 50 50 ns t dvwh t ds data setup time min 25 30 45 50 50 ns t whdx t dh data hold time min 0 ns t oes output enable setup time min 0 ns t ghwl t ghwl read recover time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 30 35 45 50 50 ns t whwl t wph write pulse width high min 20 ns t whwh1 t whwh1 byte programming operation (note 2) ty p 7 s t whwh2 t whwh2 sector erase operation (note 2) typ 1 sec t vcs v cc set up time (note 1) min 50 s
22 am29f040b preliminary oe# we# ce# v cc data addresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph t vcs 555h pa pa read status data (last two cycles) a0h t ghwl t cs status d out program command sequence (last two cycles) t ch pa note: pa = program address, pd = program data, d out is the true data at the program address. 21445b-14 figure 9. program operation timings oe# ce# addresses v cc we# data 2aah sa t ghwl t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase 30h t ds t vcs t cs t dh 55h t ch in progress complete t whwh2 va va erase command sequence (last two cycles) read status data note: sa = sector address. va = valid address for reading status data. 21445b-15 figure 10. chip/sector erase operation timings
am29f040b 23 preliminary ac characteristics we# ce# oe# high z t oe high z dq7 dq0?q6 complement tr u e addresses va t oeh t ce t ch t oh t df va va status data complement status data tr u e valid data valid data t acc t rc note: va = valid address. illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle . 21445b-16 figure 11. data# polling timings (during embedded algorithms) we# ce# oe# high z t oe dq6/dq2 addresses va t oeh t ce t ch t oh t df va va t acc t rc valid data valid status valid status (first read) (second read) (stops toggling) valid status va note: va = valid address; not required for dq6. illustration shows first two status cycle after command sequence, last status read cy cle, and array data read cycle. 21445b-17 figure 12. toggle bit timings (during embedded algorithms)
24 am29f040b preliminary ac characteristics ac characteristics erase and program operations alternate ce# controlled writes notes: 1. not 100% tested. 2. see the erase and programming performance section for more information. note: both dq6 and dq2 toggle with oe# or ce#. see the text on dq6 and dq2 in the write operation status section for more information. 21445b-18 figure 13. dq2 vs. dq6 enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 dq2 and dq6 toggle with oe# and ce# erase complete erase suspend suspend program resume embedded erasing parameter symbols description speed options unit jedec standard -55 -70 -90 -120 -150 t avav t wc write cycle time (note 1) min 55 70 90 120 150 ns t avel t as address setup time min 0 ns t elax t ah address hold time min 40 45 45 50 50 ns t dveh t ds data setup time min 25 30 45 50 50 ns t ehdx t dh data hold time min 0 ns t ghel t ghel read recover time before write min 0 ns t wlel t ws ce# setup time min 0 ns t ehwh t wh ce# hold time min 0 ns t eleh t cp write pulse width min 30 35 45 50 50 ns t ehel t cph write pulse width high min 20 20 20 20 20 ns t whwh1 t whwh1 byte programming operation (note 2) ty p 7 s t whwh2 t whwh2 sector erase operation (note 2) typ 1 sec
am29f040b 25 preliminary ac characteristics erase and programming performance notes: 1. typical program and erase times assume the following conditions: 25 c, 5.0 v v cc , 1,000,000 cycles. additionally, programming typicals assume checkerboard pattern. 2. under worst case conditions of 90c, v cc = 4.5 v (4.75 v for -55), 1,000,000 cycles. 3. the typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum byte program time listed. if the maximum byte program time given is exceeded, only then does the device set dq5 = 1. see the section on dq5 for further information. 4. in the pre-programming step of the embedded erase algorithm, all bytes are programmed to 00h before erasure. 5. system-level overhead is the time required to execute the four-bus-cycle command sequence for programming. see table 4 for further information on command definitions. 6. the device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles. parameter typ (note 1) max (note 2) unit comments sector erase time 1 8 sec excludes 00h programming prior to erasure (note 4) chip erase time 8 64 sec byte programming time 7 300 s excludes system-level overhead (note 5) chip programming time (note 3) 3.6 10.8 sec t ghel t ws oe# ce# we# t ds data t ah addresses t dh t cp dq7# d out t wc t as t cph pa data# polling a0 for program 55 for erase t rh t whwh1 or 2 t wh pd for program 30 for sector erase 10 for chip erase 555 for program 2aa for erase pa for program sa for sector erase 555 for chip erase t busy notes: 1. pa = program address, pd = program data, sa = sector address, dq7# = complement of data input, d out = array data. 2. figure indicates the last two bus cycles of the command sequence. 21445b-19 figure 14. alternate ce# controlled write operation timings
26 am29f040b preliminary latchup characteristics includes all pins except v cc . test conditions: v cc = 5.0 v, one pin at a time. tsop pin capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. plcc and pdip pin capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. data retention min max input voltage with respect to v ss on all i/o pins C1.0 v v cc + 1.0 v v cc current C100 ma +100 ma parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 6 7.5 pf c out output capacitance v out = 0 8.5 12 pf c in2 control pin capacitance v in = 0 7.5 9 pf parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 4 6 pf c out output capacitance v out = 0 8 12 pf c in2 control pin capacitance v pp = 0 8 12 pf parameter test conditions min unit minimum pattern data retention time 150 c 10 years 125 c 20 years
am29f040b 27 preliminary physical dimensions pd 032 32-pin plastic dip (measured in inches) pl 032 32-pin plastic leaded chip carrier (measured in inches) pin 1 i.d. 1.640 1.670 .530 .580 .005 min .045 .065 .090 .110 .140 .225 .120 .160 .016 .022 seating plane .015 .060 16-038-s_ag pd 032 ec75 5-28-97 lv 32 17 16 .630 .700 0 10 .600 .625 .009 .015 .050 ref. .026 .032 top view pin 1 i.d. .485 .495 .447 .453 .585 .595 .547 .553 16-038fpo-5 pl 032 da79 6-28-94 ae side view seating plane .125 .140 .009 .015 .080 .095 .042 .056 .013 .021 .400 ref. .490 .530
28 am29f040b preliminary physical dimensions (continued) ts 032 32-pin standard thin small package (measured in millimeters) pin 1 i.d. 1 18.30 18.50 7.90 8.10 0.50 bsc 0.05 0.15 0.95 1.05 16-038-tsop-2 ts 032 da95 3-25-97 lv 19.80 20.20 1.20 max 0.50 0.70 0.10 0.21 0 5 0.08 0.20
am29f040b 29 preliminary physical dimensions (continued) tsr032 32-pin reversed thin small outline package (measured in millimeters) 1 18.30 18.50 19.80 20.20 7.90 8.10 0.50 bsc 0.05 0.15 0.95 1.05 16-038-tsop-2 tsr032 da95 3-25-97 lv pin 1 i.d. 1.20 max 0.50 0.70 0.10 0.21 0 5 0.08 0.20
30 am29f040b preliminary revision summary for am29f040b global formatted for consistency with other 5.0 volt-only data data sheets. revision b+1 ac characteristics, erase and program operations added note references to t whwh1 . corrected the pa- rameter symbol for v cc set-up time to t vcs ; the spec- ification is 50 m s minimum. deleted the last row in table. revision b+2 distinctive characteristics changed minimum 100k write/erase cycles guaran- teed to 1,000,000. ordering infomation added extended temperature availability to the -55 and -70 speed options. ac characteristics erase/program operations; erase and program oper- ations alternate ce# controlled writes: corrected the notes reference for t whwh1 and t whwh2 . these param- eters are 100% tested. corrected the note reference for t vcs . this parameter is not 100% tested. erase and programming performance changed minimum 100k program and erase cycles guaranteed to 1,000,000. trademarks copyright ? 1998 advanced micro devices, inc. all rights reserved. amd, the amd logo, and combinations thereof are registered trademarks of advanced micro devices, inc. expressflash is a trademark of advanced micro devices, inc. product names used in this publication are for identification purposes only and may be trademarks of their respective companies .

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